Method and apparatus to enhance testability of logic coupled to IO buffers

ABSTRACT

A circuit to analyze or test a first or second logic coupled to an input/output circuit by storing a plurality of signals into a plurality of flip flops. The flip flops store the plurality of signals for a first mode of operation to observe at least one node within the first logic. Also, the flip flops load data values in response to control logic for a second mode of operation to control at least one node within the second logic.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to design for test improvements,and specifically to a method and apparatus for increased ability toobserve and control logic nodes located between input/output buffers anda first set of flops within a core of the integrated device.

[0003] 2. Description of the Related Art

[0004] As the technology for manufacturing integrated circuits advances,more logic functions are included in a single integrated circuit device.Modern integrated circuit (IC) devices include large numbers of gates ona single semiconductor chip, with these gates interconnected so as toperform multiple and complex functions. The fabrication of an ICincorporating such Very Large Scale Integration (VLSI) must be errorfree, as a manufacturing defect may prevent the IC from performing allof the functions that an IC is designed to perform. Such demands requireverification of the design of the IC and also various types ofelectrical testing after the IC is manufactured.

[0005] However, as the complexity of the IC increases, so does the costand complexity of verifying and electrically testing each of the devicesin the IC. Electrical testing ensures that each node in a VLSI circuitfunctions properly. Therefore, each node needs to individually, and inconjunction with the other node in the IC, function properly in allpossible combinations of operations. Typically, electrical testing isperformed by automated testing equipment (ATE) that employs test vectorsto perform the desired tests. A test vector describes the desired testinput (or signals), associated clock pulse (or pulses), and expectedtest output (or signals) for every package pin during a period of time,often in an attempt to “test” a particular node. For complex circuitry,this may involve a large number of test vectors and, accordingly, a longtest time.

[0006] One way to address this problem is through design for test (DFT).The key concepts in DFT are controllability and observability.Controllability is the ability to set and reset the state of every nodein the IC. Observability is the ability to observe either directly orindirectly the state of any node in the IC. The purpose of DFT is toincrease the ability to control and observe internal and external nodesfrom external inputs/outputs.

[0007] DFT methods utilize various test circuits. One type of testcircuit is a scan path or a scan loop in the logic circuit. A scan pathor scan loop comprises of a chain of synchronously clocked master/slavelatches (or registers), each of which is connected to a particular nodein the logic circuit. Typical scan circuit designs involve two or moreseparate scan paths or scan loops. The scan latches can be loaded with aserial data stream of scan vectors that set the logic circuit nodes to apredetermined state. The logic circuit then can be operated in normalfashion and the result of the operation is stored in its respectivelatch. A scan out operation serially unloads the contents of the latchesand the result of the test operation at the associated nodes is analyzedfor improper node operation.

[0008] The load and scan out operations are performed via a test port.One example of a test port is a defined by the Institute of Electricaland Electronic Engineers(IEEE) is a Joint Test Action Group (JTAG) testprotocols set forth in IEEE standard 1149.1. In such a system, a JTAGtest device is connected to a pair of ICs or to a single IC. The JTAGdevice generates test commands for testing the ICs. Input and output ofJTAG test commands is achieved through a set of JTAG-dedicated pinsprovided on each IC to be tested. Typically, the JTAG test device isemployed to perform scan test. General information regarding JTAG andscan test strategies and implementations may be found in “Boundary-ScanTest, A Practical Approach”, by Harry Bleeker, Peter Van Den Eijnden andFrans de Jong, Kluwer Academic publishers 1993.

[0009] Testing costs and complexity increase dramatically because of theincreasing number of functional pins on the integrated devices. Onesolution for reducing test costs is to use test equipment with acapability to only test a limited number of pins with a limited numberof test channels. However, testing and fault coverage suffers because ofthe inability to control and observe various logic nodes within theintegrated device due to the lack of dedicated tester channels.Specifically, input/output buffers require a large number of testerchannels and suffer from a lack of fault coverage because of a lack ofobservability and controllability for logic coupled to the input/outputbuffers.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0010] The present invention is illustrated by way of example and notlimitation in the following figures. Like references indicate similarelements, in which:

[0011]FIG. 1 illustrates a block diagram utilized by an embodiment ofthe present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0012] A method and apparatus to observe and control logic nodes locatedbetween input/output buffers and a first set of flops within a core ofthe integrated device are described. In the following description, forpurposes of explanation, numerous details are set forth in order toprovide a thorough understanding of the present invention. However, itwill be apparent to one skilled in the art that these specific detailsare not required in order to practice the present invention.

[0013]FIG. 1 illustrates a block diagram 100 utilized by an embodimentof the present invention. The block diagram 100 comprises a logic block102 and an input/output buffer block 104 of an integrated device. In oneembodiment, the logic block 102 and the input/output buffer 104 resideon the same integrated device. The logic block 102 comprisescombinational logic 106 and 108, flip flops 110 and 112 and controllogic 114. The input/output buffer receives as input a plurality ofsignals 116 from the logic block 102 via the combinational logic 106.The input/output buffer comprises 10 logic 118 and 120 to send andreceive data via an 10 pad 140. Also, in one embodiment the input/outputbuffer comprises a plurality of flip flops 122 and a multiplexer 124.

[0014] In another embodiment, the plurality of flip flops 122 are not inthe input/output buffer, but are coupled to the input/output buffer. Theinput/output buffer forwards data to the combinational logic block 108via the multiplexer 124.

[0015] In one embodiment, the logic block 102 processes various commandsand calculations and the input/output buffer transmits and receives dataand commands via the 10 pad. The plurality of input signals 116 to theinput/output buffer 104 from the logic block 102 is coupled to theplurality of flip flops 122(SFF1-SFFn). Each flip flop 122 has a datainput (DI), a scan in (SI) input, a scan select control (SS) input, andan output, Q. In one embodiment, each input signal 116 is coupled to asingle data input of the flip flops 122. In another embodiment, a subsetof input signals is coupled to a single data input of the flip flops122. An output, Q, of the first flip flop (SFF1) 122 is coupled to thescan input of the second flip flop (SFF2) 122. Each successive scaninput of a flip flop 122 is connected to the output, Q, of the precedingflip flop 122. Thus, the plurality of flip flops 122 forms a scan chain.In one embodiment, the output, Q, of flip flop (SFFn) 122 is connectedto one input of a multiplexer 124 and to the control logic 114. Inanother embodiment, a plurality of multiplexers 124 are individuallyconnected to one of an output of the flip flops 122 and the outputs ofthe multiplexers are connected to various nodes within the combinationallogic 108.

[0016] The control logic 114 enables and supervises the operation of theflip flops 122. The control logic 114 asserts the scan select (SS) todetermine which input, either the data input or the scan input, the flipflop 122 should receive. Also, the control logic 114 forwards the valuefor the scan input of each flip flop 122. However, the data input ofeach flip flop 122 is received from the plurality of signals 116. Theflip flops 122 form a scan chain and the control logic observes thevalues stored in the flip flops 122 since the output, Q, of the lastflip flop 122 is coupled to the control logic at node 142. In oneembodiment, the control logic 114 resides on the integrated device andis capable of receiving control signals from an Automatic Test Equipment(ATE). In another embodiment, the control logic 114 resides on anexternal integrated device, or in software, or on the ATE.

[0017] During normal operation of the integrated device, the flip flops122 store the values of the plurality of signals 116, which theinput/output buffer block 104 receives from the combinational logic 106.The control logic 114 has the ability to observe the values stored inthe flip flops 122 via node 142. Due to the ability to observe thevalues stored in the flip flops 122, the detection of errors from theplurality of signals 116 are isolated because the value is stored in theflip flop 122. Thus, there is increased fault coverage of the logicnodes within the combinational logic 106.

[0018] During a scan operation of the integrated device, the scan inputof the first flip flop 122 receives a data value from the control logic114. Since the flip flops 122 are coupled in a scan chain, the remainingflip flops 122 receive at the scan input a data value from the precedingflip flop. In one embodiment, the control logic 114 determines theplurality of input values to store in the flip flops 122 in order tocontrol a plurality of logic nodes within the combinational logic 108.In yet another embodiment, logic simulation software determines thevalues, which are forwarded to the control logic 114 via a package pin.The flip flops 122 stores the plurality of data values and the controllogic 114 instructs the multiplexer 124 to select the input coupled tothe output, Q, of the last flip flop 122 rather than the input from thefunctional 10 logic. Thus, the multiplexer forwards the data values fromthe flip flops 122 to the combinational logic 108. If one or more logicnodes within the combinational logic 108 have stuck at fault defect of a“0” value, the flip flops 122 can store a “1” value and the multiplexer124 forwards the “1” value to the particular nodes in the combinationallogic 108. The prior example was for a stuck at fault, however, theinvention is capable of detecting any manufacturing defect because ofthe ability of controlling and observing the various logic nodes inblock diagram 100. Thus, the fault coverage of the integrated deviceincreases due to the controllability of the logic nodes within thecombinational logic 108 via the flip flops 122. The controllability andobservability features of the flip flops 122 can support the integrateddevice for a variety of modes of operation including Logic Bist (LBIST)and bum in mode for reliability.

[0019] The number of flip flops 122 can vary for each cell instance ofthe input/output buffer 104 or in response to a fault coverage or diearea specification. In one embodiment, the number of flip flops 122 isequal to the number of signals 116 received in the input/output buffer104 from the combinational logic 106. Also, each different cell instanceof the input/output buffer 104 could have different numbers of flipflops 122. In another embodiment, the number of flip flops 122 is asubset of the number of signals 116 received in the input/output buffer104 from the combinational logic 106. A designer selects a subset ofsignals 116 to store based on design priority, test coveragerequirements, and die area requirements. For example, if some of thesignals 116 are controlled or observed via other test methods or storedin other flip flops, the designer can decide not to store those signalsin flip flops 122.

[0020] One skilled in the art would appreciate utilizing variousembodiments. For example, the control logic 114 controls only a subsetof the flip flops 122. Also, some of the flip flops 122 will only have adata input. In another embodiment, the control logic 114 loads newvalues into the flip flops 122 in response to a pre-determined series ofdata values observed in the flip flops 122. For example, a data value ofall logic 1 values stored in the flip flops 122 is known to eventuallyresult in an error condition, the control logic 114 asserts the scaninput of the flip flops and loads in a series of data values to preventthe error condition. In yet another embodiment, the flip flops 122observe and control logic nodes within combinational logic located onanother integrated device or system.

[0021] While the invention has been described with reference to specificmodes and embodiments, for ease of explanation and understanding, thoseskilled in the art will appreciate that the invention is not necessarilylimited to the particular features shown herein, and that the inventionmay be practiced in a variety of ways that fall under the scope andspirit of this disclosure. The invention is, therefore, to be affordedthe fullest allowable scope of the claims that follow.

1. A method for testing an integrated device comprising: receiving aplurality of signals from a first logic into an input/output circuit ofthe integrated device; storing the plurality of signals in a pluralityof flip flops in a first mode of operation to observe at least one of aplurality of logic nodes within the first logic; and controlling theplurality of flip flops with a second logic.
 2. The method of claim 1further comprising: multiplexing between an output of the plurality offlip flops and a signal in response to a control signal from the secondlogic; and loading the plurality of flip flops with a plurality of datavalues in a second mode of operation to control at least one of aplurality of logic nodes within a third logic coupled to theinput/output circuit.
 3. The method of claim 1 wherein the first mode ofoperation is a normal mode of operation for the integrated device. 4.The method of claim 1 wherein the second mode of operation is a scanoperation in response to a scan control signal from the second logic. 5.The method of claim 1 wherein the plurality of flip flops stores everydata value of the plurality of signals.
 6. The method of claim 1 whereinthe plurality of flip flops stores a subset of the data values of theplurality of signals.
 7. The method of claim 1 wherein the first andthird logic is between the input/output circuit and a functional core ofthe integrated device.
 8. An apparatus for analyzing an integrateddevice comprising: a first and a second logic; an input/output buffercircuit coupled to the first and second logic, to receive a plurality ofsignals from the first logic; a plurality of flip flops to store thedata values of the plurality of signals for a first mode of operation toobserve at least one of a plurality of logic nodes within the firstlogic; and a control logic, coupled to the input/output buffer circuit,to enable the plurality of flip flops.
 9. The apparatus of claim 8further comprising the plurality of flip flops to load a plurality ofdata values in response to a second mode of operation to control atleast one of a plurality of logic nodes within the second logic.
 10. Theapparatus of claim 8 wherein the first mode of operation is a normalmode of operation for the integrated device.
 11. The apparatus of claim8 wherein the first and second logic is between the input/output circuitand a functional core of the integrated device.
 12. The apparatus ofclaim 9 wherein the second mode of operation is a scan mode of operationenabled by the control logic.
 13. An apparatus for analyzing anintegrated device comprising: a first and a second logic; aninput/output buffer circuit coupled to the first and second logic, toreceive a plurality of signals from the second logic in a first mode ofoperation; a control logic, coupled to the input/output buffer circuit,to load a plurality of flip flops with a plurality of data values inresponse to a second mode of operation to control at least one of aplurality of logic nodes within the first logic.
 14. The apparatus ofclaim 13 wherein the input/output circuit comprises a plurality of flipflops store a subset of data values of the plurality of signals to allowan observation of at least one logic node within the second logic. 15.The apparatus of claim 13 wherein the first mode of operation is anormal mode of operation for the integrated device.
 16. The apparatus ofclaim 13 wherein the first and second logic is between the input/outputcircuit and a functional core of the integrated device.
 17. Theapparatus of claim 13 wherein the second mode of operation is a scanmode of operation enabled by the control logic 1.